Nonlinear Codes for Error Detection and Correction in Reliable Memory Systems

Linear single-error-correcting, double-error-detecting (SEC-DED) codes used for design of reliable memories cannot detect and can miscorrect some errors with large Hamming weights. In this paper we present several constructions of optimal nonlinear robust and partially robust codes, i.e. the Vasil’ev codes, the Phelps codes and the codes based on one switching constructions. The error detection and correction capabilities of these codes are analyzed and compared. We propose protection for memory devices based on extended Vasil’ev codes and extended Phelps codes. These nonlinear SEC-DEC codes have a minimum distance of four, fewer undetectable errors and fewer errors that are miscorrected than linear codes with the same dimension and redundancy. The extended Vasil’ev codes and the extended Phelps codes can provide for higher reliability in the presence of repeating errors or high rate of multi-bit-upsets. In this case replacing extended Hamming codes by the proposed codes may result in a drastic improvement in reliability of the memory with a reasonable cost in hardware overhead and power consumption. The architectures of memories based on these codes are described and the simulation results are presented illustrating their advantages over linear extended Hamming codes. Simple decoding algorithms for the nonlinear codes that can be used to provide concurrent error correction are presented. The proposed approach can be applied to RAM, ROM, FLASH and disk memories.